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-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:40:58 04/15/2011 
-- Design Name: 
-- Module Name:    sp - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sp is
    Port ( sp_clk    : in  STD_LOGIC;
           sp_enable : in  STD_LOGIC;
           we        : in  STD_LOGIC; -- we stack
           sp_in     : in  STD_LOGIC_VECTOR (2 downto 0); -- a_out stack
           sp_out    : out  STD_LOGIC_VECTOR (2 downto 0)); -- a_in stack
end sp;

architecture Behavioral of sp is
begin
	process (sp_clk, sp_enable, we)
	begin
		if rising_edge (sp_clk) then
			if sp_enable = '1' then
				if we = '1' then
				   if sp_in = "111" then -- trato de escribir en la cima de la pila
						sp_out <= "000";
					else
						sp_out <= sp_in + ext("001",3);
					end if;
				else
				    if sp_in = "000" then -- trato de leer en el fondo de la pila
						sp_out <= "111";
					else
						sp_out <= sp_in - ext("001",3);
					end if;
				end if;
			end if;
		end if;
	end process;
end Behavioral;

